1. Field of the Invention
The present invention relates to a semiconductor device using an SOI substrate and its manufacturing method.
2. Description of the Background Art
An SOI substrate has a semiconductor substrate, an insulating layer, and a semiconductor layer of a first conductivity type which are stacked in this order. A method for manufacturing a conventional semiconductor device using an SOI substrate includes the steps of: (a) forming an element-isolation insulating film of a so-called partial isolation type in portions in an upper surface of a semiconductor layer; (b) in an element formation region, forming a gate structure on a portion of the upper surface of the semiconductor layer; and (c) ion-implanting impurities into the upper surface of the semiconductor layer to form source/drain regions of a second conductivity type that extend from the upper surface of the semiconductor layer to reach the insulating layer. The steps (a) to (c) are performed in this order.
A technique about a semiconductor device using an SOI substrate and a method for manufacturing the same are disclosed in Japanese Patent Application Laid-Open No. 10-209167 (1998).
In the conventional semiconductor device manufacturing method, when the ion implant energy is increased to cause the source/drain regions to reach the insulating layer, then the second conductivity type impurities are implanted into the portions of the semiconductor layer that are located between the bottom surface of the element-isolation insulating film and the top surface of the insulating layer. Then the first conductivity type concentration in those portions is lowered, which lowers the isolation breakdown voltage.
When, in order to solve this problem, the ion implant energy is lowered so that impurities will not penetrate through the element-isolation insulating film, the source/drain regions will not reach the insulating layer and the junction capacitance of the source/drain regions will increase. This causes problems, such as reduced operating speed and increased power consumption.
Also, in order to solve the problem, when the element-isolation insulating film is formed deep so that its bottom surface is located close to the top surface of the insulating layer, then the resistance value of the semiconductor layer will increase in the portions located between the bottom surface of the element-isolation insulating film and the top surface of the insulating layer.
Also, in order to solve the problem, when the element-isolation insulating film is formed thick so that its top surface is located extremely higher than the top surface of the semiconductor layer, then the large difference in height between the top surface of the element-isolation insulating film and the top surface of the semiconductor layer makes it difficult to accurately form the gate electrode. This will cause problems, such as reduction of operating speed and variation of characteristics.